1. Field of the Invention
The present invention relates to a tolerance input/output circuit, and more specifically, to a tolerance input/output circuit operating from a single power supply.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional tolerance input/output circuit. The circuit includes five blocks 10, 20, 30, 40 and 50.
Block 10 generates a correction signal 102, at a level appropriate to the characteristics of a given device, to a Y gate `Y` and to one of the input terminals of block 20. This correction signal 102 is derived from pad signal 101 which is applied to a PAD and passed through a resistor.
Block 20 receives the correction signal 102 and an enable signal 201, generating an inverted correction signal 102b and an inverted enable signal 201b.
Block 30 generates a P gate signal 301 depending on whether the circuit is in an input or output mode. Block 30 receives the inverted correction signal 102b, the inverted enable signal 201b and the pad signal 101.
Block 40 is for generating a kilpoly signal 401. It receives the pad signal 101 and the inverted correction signal 102b.
Block 50 receives N gate signal 501 and P gate signal 301, generating a pad signal 502 depending on whether it is in an input or output mode. This pad signal 502 is fed back as the pad signal 101.
FIGS. 2 and 3 show voltage and current characteristics when the pad input voltage is swung from 0V to 5.5V, in the conventional tolerance input/output circuit of FIG. 1. As shown in FIGS. 2 and 3, when the pad voltage is swung to 5.5V, forward-biased diode formed on each source region. The bulk of PMOS transistors included in Block 40 reduces the response speed of the voltage characteristics of the kilpoly signal 401 and generates much leakage current in the substrate.